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HY5DU281622ET
128M(8Mx16) GDDR SDRAM
HY5DU281622ET
This document is a general product description and is subject to change without notice. Hynix Electronics does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 0.5 / Jan. 2005 1
HY5DU281622ET
Revision History
Revision No. 0.1 0.2 0.3 0.4 0.5 Defined target spec. 1) Insert Overshoot/Undershoot Specification 2) Insert tDSS/tDSH Parameter tPDEX value Change tRC_APCG changed to 12 clock from 11 clock at 166Mhz speed bin 166Mhz speed bin delete, AC parameter change (tRC_APCG at 200Mhz) History Draft Date July 2003 Oct. 2003 Mar. 2004 Oct. 2004 Jan. 2005 Remark
Rev. 0.5 / Jan. 2005
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HY5DU281622ET
DESCRIPTION
The Hynix HY5DU281622ET is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which require high densities and high bandwidth. The Hynix 8Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
FEATURES
* * * * * * * * 2.8V +/- 0.1V VDD and VDDQ power supply supports 400/375/350/333/300MHz 2.5V +/- 5% VDD and VDDQ power supply supports 275/250/200/166MHz All inputs and outputs are compatible with SSTL_2 interface JEDEC Standard 400 mil x 875 mil 66 Pin TSOP II, with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (UDQS,LDQS) Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) Data(DQ) and Write masks(DM) latched on the both * * * * * * * * rising and falling edges of the data strobe * All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Write mask byte controls by DM (UDM,LDM) Programmable /CAS Latency 5, 4 and 3 are supported Programmable Burst Length 2, 4 and 8 with both sequential and interleave mode Internal 4 bank operation with single pulsed /RAS tRAS Lock-Out function are supported Auto refresh and self refresh are supported 4096 refresh cycles / 32ms Full strength, Half strength and Weak Impedance driver options controlled by EMRS
*
ORDERING INFORMATION
Part No. HY5DU281622ET-25 HY5DU281622ET-26 HY5DU281622ET-28 HY5DU281622ET-30 HY5DU281622ET-33 HY5DU281622ET-36 HY5DU281622ET-4 HY5DU281622ET-5 VDD/VDDQ=2.5V VDD/VDDQ=2.8V Power Supply Clock Frequency 400MHz 375MHz 350MHz 333MHz 300MHz 275MHz 250MHz 200MHz Max Data Rate 800Mbps/pin 750Mbps/pin 700Mbps/pin 666Mbps/pin 600Mbps/pin 550Mbps/pin 500Mbps/pin 400Mbps/pin SSTL_2 400 x 875mil 2 66 Pin TSOP II interface Package
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HY5DU281622ET
PIN CONFIGURATION (Top View)
VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDDQ LDQS NC VDD NC LDM /WE /CAS /RAS /CS NC BA0 BA1 A10/AP A0 A1 A2 A3 VDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
400mil X 875mil 66pin TSOP -II 0.65mm pin pitch
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 NC VSSQ UDQS NC VREF VSS UDM /CK CK CKE NC NC A11 A9 A8 A7 A6 A5 A4 VSS
ROW AND COLUMN ADDRESS TABLE
ITEMS
Organization Row Address Column Address Bank Address Auto Precharge Flag Refresh
8Mx16
2M x 16 x 4banks A0 - A11 A0-A8 BA0, BA1 A10 4K
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HY5DU281622ET
PIN DESCRIPTION
PIN CK, /CK TYPE Input DESCRIPTION Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry and exit. CKE is asynchronous for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied. Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered. Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15 Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15 Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection.
CKE
Input
/CS
Input
BA0, BA1
Input
A0 ~ A11
Input
/RAS, /CAS, /WE
Input
UDM, LDM
Input
UDQS, LDQS DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ VREF NC
I/O I/O Supply Supply Supply NC
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HY5DU281622ET
FUNCTIONAL BLOCK DIAGRAM
4Banks x 2Mbit x 16 I/O Double Data Rate Synchronous DRAM
16
Input Buffer
Write Data Register 2-bit Prefetch Unit
DS
32
CLK
Bank Control
/CLK
CKE
2Mx16/Bank0
2-bit Prefetch Unit
Sense AMP
Output Buffer
/CS
/RAS
2Mx16/Bank1
32
16
Command Decoder
2Mx16/Bank2
2Mx16/Bank3
Mode Register
/CAS
/WE
LDM UDM
DQ[0:15]
Row Decoder
Column Decoder
LDQS, UDQS
A0~A11
CLK_DLL Address Buffer BA0, BA1
Column Address Counter
Data Strobe Transmitter
LDQS UDQS CLK /CLK
DLL Block
Data Strobe Receiver
Mode Register
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SIMPLIFIED COMMAND TRUTH TABLE
Command Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit CKEn-1 H H H H H CKEn X X X X X CS L L H L L L RAS L L X H L H CAS L L X H H L WE L L X H H H CA RA L H L H H L X X
ADDR
A10/ AP OP code OP code X
BA
Note 1,2 1,2 1
V V
1 1 1,3 1 1,4 1,5 1 1 1 1
H
X
L
H
L
L
CA
V X V
H H H H L
X X H L H
L L L L H L H L H L H L
L H L L X H X H X H X V X
H H L L X H X H X H X V
L L H H X H X H X H X V
X
X
1 1
Entry Precharge Power Down Mode Exit
H
L
X
1 1 1 1
L
H
Active Power Down Mode
Entry Exit
H L
L H
X
1 1
( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. UDM, LDM states are Don't Care. Refer to below Write Mask Truth Table.(note 6) 2. OP Code(Operand Code) consists of A0~A11 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented to activate bank until CK(n+BL/2+tRP). 4. If a Write with Auto-precharge command is detected by memory component in CK(n), then there will be no command presented to activate bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time(tWR) is needed to guarantee that the last data have been completely written. 5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged. 6. In here, Don't Care means logical value only, it doesn't mean 'Don't care for DC level of each signals'. DC level should be out of VIHmin ~ VILmax Rev. 0.5 / Jan. 2005 7
HY5DU281622ET
WRITE MASK TRUTH TABLE
Function Data Write Data-In Mask CKEn-1 H H CKEn X X /CS, /RAS, /CAS, /WE X X DM L H
ADDR
A8/ AP X X
BA
Note
1,2,3 1,2,3
Note : 1. Write Mask command masks burst write data with reference to UDQS/LDQS and it is not related with read data. 2. LDM corresponds to the data on DQ0-Q7 and UDM corresponds to the data on DQ8-Q15 3. In here, Don't Care means logical value only, it doesn't mean 'Don't care for DC level of each signals'. DC level should be out of VIHmin ~ VILmax
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OPERATION COMMAND TRUTH TABLE - I
Current State /CS H L L L IDLE L L L L L H L L L ROW ACTIVE L L L L L H L L L READ L L L L L H L WRITE L L L Rev. 0.5 / Jan. 2005 /RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H /CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L /WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP Action NOP or power down3 NOP or power down3 ILLEGAL4 ILLEGAL4 ILLEGAL4 Row Activation NOP Auto Refresh or Self Refresh5 Mode Register Set NOP NOP ILLEGAL4 Begin read : optional AP6 Begin write : optional AP6 ILLEGAL4 Precharge7 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end Terminate burst Term burst, new read:optional AP8 ILLEGAL ILLEGAL4 Term burst, precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL4 Term burst, new read:optional AP8 Term burst, new write:optional AP 9
HY5DU281622ET
OPERATION COMMAND TRUTH TABLE - II
Current State /CS L WRITE L L L H L L READ WITH AUTOPRECHARGE L L L L L L H L L WRITE AUTOPRECHARGE L L L L L L H L L L PRECHARGE L L L L L /RAS L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L /CAS H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L /WE H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Address BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE Command ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL4 Term burst, precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 NOP-Enter IDLE after tRP NOP-Enter IDLE after tRP ILLEGAL4 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,10 NOP-Enter IDLE after tRP ILLEGAL11 ILLEGAL11
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HY5DU281622ET
OPERATION COMMAND TRUTH TABLE - III
Current State /CS H L L L ROW ACTIVATING L L L L L H L L L WRITE RECOVERING L L L L L H L L WRITE RECOVERING WITH AUTOPRECHARGE L L L L L L H L REFRESHING L L /RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H /CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L /WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP Action NOP - Enter ROW ACT after tRCD NOP - Enter ROW ACT after tRCD ILLEGAL4 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,9,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 NOP - Enter ROW ACT after tWR NOP - Enter ROW ACT after tWR ILLEGAL4 ILLEGAL ILLEGAL ILLEGAL4,10 ILLEGAL4,11 ILLEGAL11 ILLEGAL11 NOP - Enter precharge after tDPL NOP - Enter precharge after tDPL ILLEGAL4 ILLEGAL4,8,10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,11 ILLEGAL11 ILLEGAL11 NOP - Enter IDLE after tRC NOP - Enter IDLE after tRC ILLEGAL11 ILLEGAL11
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HY5DU281622ET
OPERATION COMMAND TRUTH TABLE - IV
Current State /CS L L WRITE L L L H L L L MODE REGISTER ACCESSING L L L L L /RAS H L L L L X H H H H L L L L /CAS L H H L L X H H L L H H L L /WE L H L H L X H L H L H L H L Address BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE Command WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 NOP - Enter IDLE after tMRD NOP - Enter IDLE after tMRD ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11
Note : 1. H - Logic High Level, L - Logic Low Level, X - Don't Care, V - Valid Data Input, BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation.(see note 12) 2. All entries assume that CKE was active(high level) during the preceding clock cycle. 3. If both banks are idle and CKE is inactive(low level), then in power down mode. 4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of that bank. 5. If both banks are idle and CKE is inactive(low level), then self refresh mode. 6. Illegal if tRCD is not met. 7. Illegal if tRAS is not met. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Illegal if tRRD is not met. 10. Illegal for single bank, but legal for other banks in multi-bank devices. 11. Illegal for all banks. 12. In here, Don't Care means logical value only, it doesn't mean 'Don't care for DC level of each signals'. DC level should be out of VIHmin ~ VILmax
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CKE FUNCTION TRUTH TABLE
Current State CKEn1 H L L SELF REFRESH1 L L L L H L POWER DOWN2 L L L L L H H H ALL BANKS IDLE4 H H H H H L ANY STATE OTHER THAN ABOVE H H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L /CS X H L L L L X X H L L L L X X L H L L L L L X X X X X /RAS X X H H H L X X X H H H L X X L X H H H L L X X X X X /CAS X X H H L X X X X H H L X X X L X H H L H L X X X X X /WE X X H L X X X X X H L X X X X H X H L X X L X X X X X /ADD X X X X X X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit self refresh, enter idle after tSREX Exit self refresh, enter idle after tSREX ILLEGAL ILLEGAL ILLEGAL NOP, continue self refresh INVALID Exit power down, enter idle Exit power down, enter idle ILLEGAL ILLEGAL ILLEGAL NOP, continue power down mode See operation command truth table Enter self refresh Exit power down Exit power down ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP See operation command truth table ILLEGAL5 INVALID INVALID
Note : When CKE=L, all DQ and UDQS/LDQS should be in Hi-Z state. 1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command. 2. All commands can be stored after 2 clocks from low to high transition of CKE. 3. Illegal, if CK is suspended or stopped during the power down mode. 4. Self refresh can be asserted only from the all banks idle state. 5. Disabling CK may cause malfunction of any banks which are in active state.
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HY5DU281622ET
SIMPLIFIED STATE DIAGRAM
MODE REGISTER SET
MRS
IDLE
SREF SREX
SELF REFRESH
PDEN PDEX
POWER DOWN
POWER DOWN
AREF ACT
AUTO REFRESH
PDEN
BST
BANK ACTIVE
PDEX
READ WRITE READAP
WRITE
READ
PRE(PALL)
WRITE WITH AUTOPRECHARGE
READ READAP WITH AUTOPRECHARGE WRITEAP
READ
WRITEAP
WRITE PRE(PALL) PRE(PALL)
PRECHARGE
POWER-UP
Command Input Automatic Sequence
POWER APPLIED
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POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200s delay prior to applying an executable command. Once the 200s delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Register set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation. 1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVCMOS low state. (All the other input pins may be undefined.) No power sequencing is specified during power up or power down given the following cirteria : * VDD and VDDQ are driven from a single power converter output. * VTT is limited to 1.4025V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation). * VREF tracks VDDQ/2. * If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must be adhered to during power up : Voltage description VDDQ VTT VREF 2. 3. 4. 5. 6. 7. 8. Sequencing After or with VDD After or with VDDQ After or with VDDQ Voltage relationship to avoid latch-up < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V
Start clock and maintain stable clock for a minimum of 200sec. After stable power and clock, apply NOP or DESELECT conditionS and take CKE high. Following the NOP command, a PRECHARGE ALL command should be applied Issue Extended Mode Register Set (EMRS) to enable DLL. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles(tXSRD) of clock are required for locking DLL) Issue Precharge commands for all banks of the device. Issue 2 or more Auto Refresh commands.
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9. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
Power-Up Sequence
VDD
VDDQ
tVTD
VTT VREF
/CLK CLK
tIS tIH
CKE
LVCMOS Low Level
CMD
NOP
PRE
EMRS
MRS
NOP
PRE
AREF
MRS
ACT
RD
DM
ADDR
CODE
CODE
CODE
CODE
CODE
A10
CODE
CODE
CODE
CODE
CODE
BA0, BA1
CODE
CODE
CODE
CODE
CODE
DQS
DQ'S
T=200usec tRP
tMRD
tMRD
tRP
tRFC tXSRD*
tMRD
Power UP VDD and CK stable
Precharge All
EMRS Set
MRS Set Reset DLL (with A8=H)
Precharge All
2 or more Auto Refresh
MRS Set (with A8=L)
Non-Read Command
READ
* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command
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MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is determined, the information will be held until resetted by another MRS command.
BA1 0
BA0 0
A11
A10 RFU*
A9
A8 DR
A7 TM
A6
A5
A4
A3 BT
A2
A1
A0
CAS Latency
Burst Length
BA0 0 1
MRS Type MRS EMRS
A7 0 1
Test Mode Normal Vendor test mode Burst Length A2 A1 A0 Sequential 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Reserved 2 4 8 Reserved Reserved Reserved Reserved Interleave Reserved 2 4 8 Reserved Reserved Reserved Reserved
A8 0 1
DLL Reset No Yes
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved Reserved 3 4 5 Reserved Reserved A3 0 1
0 1 1 1 1
Burst Type Sequential Interleave
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage. And, if MRS/EMRS are programmed with `Reserved' code, it could be the cause of mal-function.
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BURST DEFINITION
Burst Length 2 Starting Address (A2,A1,A0) XX0 XX1 X00 4 X01 X10 X11 000 001 010 8 011 100 101 110 111 Sequential 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 0, 1, 2, 3, 4, 5, 6, 7 Interleave 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts. Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definitionon Table
Rev. 0.5 / Jan. 2005
18
HY5DU281622ET
CAS LATENCY
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the availability of the first burst of output data. The latency can be programmed 3 or 4 clocks. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
This device supports both Half strength driver and Matched impedance driver, intended for lighter load and/or point-topoint environments. Half strength driver is to define about 50% of Full drive strength which is specified to be SSTL_2, Class II, and Matched impedance driver, about 30% of Full drive strength.
Rev. 0.5 / Jan. 2005
19
HY5DU281622ET
EXTENDED MODE REGISTER SET (EMRS)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation.
BA1 0 BA0 1 A11 A10 A9 RFU* A8 A7 A6 DS A5 A4 A3 A2 A1 DS A0 DLL
RFU*
BA0 0 1
MRS Type MRS EMRS
A0 0 1
DLL enable Enable Diable
A6 0 0 1 1
A1 0 1 0 1
Output Driver Impedance Control Full Half (60%) Reserved Weak (33%)
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.
Rev. 0.5 / Jan. 2005 20
HY5DU281622ET
ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Output Short Circuit Current Power Dissipation Soldering Temperature Time
Symbol
TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER
Rating
0 ~ 70 -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 50 2 260 10
Unit
oC o
C
V V V mA W
oC
sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
Parameter
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Symbol
VDD VDDQ VDD VDDQ VIH VIL VTT VREF
Min
2.375 2.375 2.7 2.7 VREF + 0.15 -0.3 VREF - 0.04 0.49*VDDQ
Typ
2.5 2.5 2.8 2.8 VREF 0.5*VDDQ
Max
2.625 2.625 2.9 2.9 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 0.51*VDDQ
Unit
V V V V V V V V
Note
1,4 1,4 1,5 1,5
Power Supply Voltage
Input High Voltage Input Low Voltage Termination Voltage Reference Voltage
3 2
Note : 1. VDDQ must not exceed the level of VDD. 2. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed 2% of the DC value. 3. VTT is expected to be set equal to VREF, and Vtt of the transmitting device must track VREF of the receiving device. 4. Supports 275/ 250/ 200/166Mhz 5. Supports 400/375/350/333/300Mhz
DC CHARACTERISTICS I
Parameter
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Symbol
ILI ILO VOH VOL
Min
-5 -5 VTT + 0.76 -
Max
5 5 VTT - 0.76
Unit
uA uA V V
Note
1 2 IOH = -15.2mA,2 IOL = +15.2mA,2
Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN =0V. 2. DOUT is disabled, VOUT=0 to 2.625V, It means, output logic high voltage and low voltage is depend on output channel conditions. Rev. 0.5 / Jan. 2005 21
HY5DU281622ET DC CHARACTERISTICS II
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Speed Parameter Symbol Test Condition 25 One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Burst length=4, One bank active tRC tRC(min), IOL=0mA 26 28 30 33 Unit
Note
Operating Current
IDD0
230
220
210
200
190
mA
1
Operating Current Precharge Standby Current in Power Down Mode Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode Burst Mode Operating Current Auto Refresh Current Self Refresh Current
IDD1
230
220
210
200
190
mA
1
IDD2P
CKE VIL(max), tCK=min
40
40
40
40
40
mA
IDD2N
CKE VIH(min), /CS VIH(min), tCK = min, Input signals are changed one time during 2clks
150
140
130
120
110
mA
IDD3P
CKE VIL(max), tCK=min
40
40
40
40
40
mA
IDD3N
CKE VIH(min), /CS VIH(min), tCK=min, Input signals are changed one time during 2clks tCK tCK(min), IOL=0mA All banks active tRC tRFC(min), All banks active CKE 0.2V Four bank interleaving with BL=4, Refer to the following page for detailed test condition
190
180
170
160
150
mA
IDD4
380
360
340
320
300
mA
1
IDD5 IDD6
380 4
360 4
340 4
320 4
300 4
mA mA
1,2
Operating Current Four Bank Operation
IDD7
530
510
490
470
450
mA
Note : 1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
Rev. 0.5 / Jan. 2005
22
HY5DU281622ET DC CHARACTERISTICS II
(TA=0 to 70oC, Voltage referenced to VSS = 0V)
Speed Parameter Symbol Test Condition 36 One bank; Active - Precharge; tRC=tRC(min); tCK=tCK(min); DQ,DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle Burst length=2, One bank active tRC tRC(min), IOL=0mA CKE VIL(max), tCK=min CKE VIH(min), /CS VIH(min), tCK = min, Input signals are changed one time during 2clks CKE VIL(max), tCK=min CKE VIH(min), /CS VIH(min), tCK=min, Input signals are changed one time during 2clks tCK tCK(min), IOL=0mA All banks active tRC tRFC(min), All banks active CKE 0.2V Four bank interleaving with BL=4, Refer to the following page for detailed test condition 4 5 Unit
Note
Operating Current
IDD0
180
170
160
mA
1
Operating Current Precharge Standby Current in Power Down Mode Precharge Standby Current in Non Power Down Mode Active Standby Current in Power Down Mode Active Standby Current in Non Power Down Mode Burst Mode Operating Current Auto Refresh Current Self Refresh Current
IDD1
180
170
160
mA
1
IDD2P
40
40
40
mA
IDD2N
100
90
80
mA
IDD3P
40
40
40
mA
IDD3N
140
130
120
mA
IDD4
280
260
240
mA
1
IDD5 IDD6
280 4
260 4
240 4
mA mA
1,2
Operating Current - Four Bank Operation
IDD7
430
410
390
mA
Note : 1. IDD1, IDD4 and IDD5 depend on output loading and cycle rates. Specified values are measured with the output open. 2. Min. of tRFC (Auto Refresh Row Cycle Time) is shown at AC CHARACTERISTICS.
Rev. 0.5 / Jan. 2005
23
HY5DU281622ET
AC OPERATING CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.45 VREF - 0.45 VDDQ + 0.6 0.5*VDDQ+0.2 Max Unit V V V V 1 2 Note
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on /CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=0 to 70oC, Voltage referenced to VSS = 0V)
Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) Value VDDQ x 0.5 VDDQ x 0.5 VREF + 0.45 VREF - 0.45 VREF VTT 1.5 1 50 25 30 Unit V V V V V V V V/ns pF
Rev. 0.5 / Jan. 2005
24
HY5DU281622ET
AC Overshoot/Undershoot specifications for Address and Command pins
Parameter Maximum peak amplitude allowwed for overshoot Maximum peak amplitude allowwed for undershoot The area between the overshoot signal and VDD must be less than or equal to(See below Fig) The area between the overshoot signal and GND must be less than or equal to(See below Fig)
Max. amplitude=1.5V +5 +4 +3
200MHz Specifications 1.5 V 1.5 V 4.5 V-nS 4.5 V-nS
Volts +2 (V) +1
0 -1 -2 Max. area=4.5V-ns -3 0 1 2 3 4 5 6
VDD
Ground
Time(ns)
AC Overshoot/Undershoot specifications for Data, Strobe and Mask Pins
Parameter Maximum peak amplitude allowwed for overshoot Maximum peak amplitude allowwed for undershoot The area between the overshoot signal and VDD must be less than or equal to(See below Fig) The area between the overshoot signal and GND must be less than or equal to(See below Fig) 200MHz Specifications 1.2 V 1.2 V 2.4 V-nS 2.4 V-nS
Max. amplitude=1.2V
+5 +4 +3
Volts +2 (V) +1
0 -1 -2
VDD
Ground
Max. area=2.4V-ns
-3 0 1 2 3 4 5 6
Time(ns)
Rev. 0.5 / Jan. 2005
25
HY5DU281622ET
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter Row Cycle Time(Manual Precharge) Row Cycle Time(Auto Precharge) Auto Refresh Row Cycle Time Row Active Time Row Address to Column Address Delay for Read Row Address to Column Address Delay for Write Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Last Data-In to Read Command Auto Precharge Write Recovery + Precharge Time System Clock Cycle Time Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Input Setup Time Input Hold Time Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Data-In Hold Time to DQS-In (DQ & DM) Rev. 0.5 / Jan. 2005 CL=5 CL=4 Symbol tRC tRC_APCG tRFC tRAS tRCDRD tRCDWR tRRD tCCD tRP tWR tDRL tDAL tCK tCH tCL tAC tDQSCK tDQSQ tQH tHP tQHS tIS tIH tDQSH tDQSL tDQSS tDS tDH
25 Min 22 24 26 16 6 4 4 2 6 4 2 10 2.5 0.45 0.45 -0.55 -0.55 tHPmin -tQHS tCH/L min 0.75 0.75 0.4 0.4 0.85 0.35 0.35 Max 100K 6 0.55 0.55 0.55 0.55 0.35 0.35 0.6 0.6 1.15 Min 21 23 25 15 6 4 4 2 6 4 2 10 2.6 0.45 0.45 -0.6 -0.6 tHPmin -tQHS tCH/L min 0.75 0.75 0.4 0.4 0.85 0.35 0.35 26 Max 100K 6 0.55 0.55 0.6 0.6 0.35 0.35 0.6 0.6 1.15 Min 20 22 24 14 6 4 4 2 6 4 2 10 2.8 0.45 0.45 -0.6 -0.6 tHPmin -tQHS tCH/L min 0.75 0.75 0.4 0.4 0.85 0.35 0.35 28
Unit Note
Max 100K 6 0.55 0.55 0.6 0.6 0.35 0.35 0.6 0.6 1.15 -
CK
CK CK CK CK CK CK CK CK CK CK ns CK CK ns ns ns ns ns ns ns ns CK CK CK ns ns
3 3 1,6 1,5 6 2 2
26
HY5DU281622ET
Parameter DQS falling edge to CK setup time DQS falling edge hold time from CK Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Power Down Exit Time Average Periodic Refresh Interval Note : 1. 2. 3. 4. 5. 6.
Symbol
tDSS
25 Min 3.0 3.0 0 0.35 0.4 10 200 2tCK + tIS Max 0.6 7.8 Min 3.0 3.0 0 0.35 0.4 10 200 2tCK + tIS -
26 Max 0.6 7.8 Min 3.0 3.0 0 0.35 0.4 10 200 2tCK + tIS -
28
Unit Note
Max 0.6 7.8
CK CK ns CK CK ns CK CK us
4
tDSH tWPRES tWPREH tWPST tMRD tXSC tPDEX tREFI
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. Data latched at both rising and falling edges of Data Strobes(UDQS,LDQS) : DQ, LDM,UDM. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic.
7.
Rev. 0.5 / Jan. 2005
27
HY5DU281622ET
AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter Row Cycle Time(Manual Precharge) Row Cycle Time(Auto Precharge) Auto Refresh Row Cycle Time Row Active Time Row Address to Column Address Delay for Read Row Address to Column Address Delay for Write Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Last Data-In to Read Command Auto Precharge Write Recovery + Precharge Time System Clock Cycle Time Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Input Setup Time Input Hold Time Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Data-In Hold Time to DQS-In (DQ & DM) CL=4 Symbol tRC tRC_APCG tRFC tRAS tRCDRD tRCDWR tRRD tCCD tRP tWR tDRL tDAL tCK tCH tCL tAC tDQSCK tDQSQ tQH tHP tQHS tIS tIH tDQSH tDQSL tDQSS tDS tDH
30 Min 19 21 23 13 6 4 4 2 6 4 2 10 3 0.45 0.45 -0.6 -0.6 tHPmin -tQHS tCH/L min 0.75 0.75 0.4 0.4 0.85 0.35 0.35 Max 100K 6 0.55 0.55 0.6 0.6 0.35 0.35 0.6 0.6 1.15 Min 18 20 22 12 6 4 4 1 6 4 2 10 3.3 0.45 0.45 -0.6 -0.6 tHPmin -tQHS tCH/L min 0.75 0.75 0.4 0.4 0.85 0.35 0.35 33 Max 100K 6 0.55 0.55 0.6 0.6 0.35 0.35 0.6 0.6 1.15 Min 16 18 20 11 5 3 3 1 5 3 2 8 3.6 0.45 0.45 -0.6 -0.6 tHPmin -tQHS tCH/L min 0.75 0.75 0.4 0.4 0.85 0.4 0.4 36
Unit Note
Max 100K 10 0.55 0.55 0.6 0.6 0.35 0.4 0.6 0.6 1.15 -
CK
CK CK CK CK CK CK CK CK CK CK ns CK CK ns ns ns ns ns ns ns ns CK CK CK ns ns
3 3 1,6 1,5 6 2 2
Rev. 0.5 / Jan. 2005
28
HY5DU281622ET
30 Min 0.3 0.3 0.9 0.4 0 0.35 0.4 10 200 2tCK + tIS Max 1.1 0.6 0.6 7.8 Min 0.3 0.3 0.9 0.4 0 0.35 0.4 10 200 2tCK + tIS 33 Max 1.1 0.6 0.6 7.8 Min 0.3 0.3 0.9 0.4 0 0.35 0.4 10 200 2tCK + tIS 36
Unit Note
Parameter DQS falling edge to CK setup time DQS falling edge hold time from CK Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Power Down Exit Time Average Periodic Refresh Interval Note : 1. 2. 3. 4. 5. 6.
Symbol
tDSS
Max 1.1 0.6 0.6 7.8
CK CK CK CK ns CK CK ns CK CK us
4
tDSH tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tPDEX tREFI
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. Data latched at both rising and falling edges of Data Strobes(UDQS,LDQS) : DQ, LDM,UDM. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic.
7.
Rev. 0.5 / Jan. 2005
29
HY5DU281622ET
AC CHARACTERISTICS - I
Parameter Row Cycle Time(Manual Precharge) Row Cycle Time(Auto Precharge) Auto Refresh Row Cycle Time Row Active Time Row Address to Column Address Delay for Read Row Address to Column Address Delay for Write Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Write Recovery Time Last Data-In to Read Command Auto Precharge Write Recovery + Precharge Time System Clock Cycle Time Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Input Setup Time Input Hold Time Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In CL=4 CL=3 (Continued)
4 Min 15 17 18 10 5 3 3 1 5 3 2 8 4 Max 100K 10 0.55 0.55 0.6 0.6 0.4 0.4 0.6 0.6 1.15 Min 12 13 14 8 4 2 2 1 4 3 2 7 5 0.45 0.45 -0.65 -0.55 tHPmin -tQHS tCH/L min 0.6 0.6 0.4 0.4 0.72 5
Unit Note
Symbol tRC tRC_APCG tRFC tRAS tRCDRD tRCDWR tRRD tCCD tRP tWR tDRL tDAL
Max 100K 10 0.55 0.55 0.65 0.55 0.4 0.45 0.6 0.6 1.28
CK
CK CK CK CK CK CK CK CK CK CK
tCK tCH tCL tAC tDQSCK tDQSQ tQH tHP tQHS tIS tIH tDQSH tDQSL tDQSS
ns CK CK ns ns ns ns ns ns ns ns CK CK CK
1,6 1,5 6 2 2
0.45 0.45 -0.6 -0.6 tHPmin -tQHS tCH/L min 0.75 0.75 0.4 0.4 0.85
Rev. 0.5 / Jan. 2005
30
HY5DU281622ET
4 Min 0.4 0.4 0.3 0.3 0.9 0.4 0 0.35 0.4 10 200 2tCK + tIS Max 1.1 0.6 0.6 7.8 Min 0.4 0.4 0.3 0.3 0.9 0.4 0 0.25 0.4 10 200 2tCK + tIS 5
Unit Note
Parameter Data-In Setup Time to DQS-In (DQ & DM) Data-In Hold Time to DQS-In (DQ & DM) DQS falling edge to CK setup time DQS falling edge hold time from CK Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Power Down Exit Time Average Periodic Refresh Interval Note : 1. 2. 3. 4. 5. 6.
Symbol tDS tDH
tDSS
Max 1.1 0.6 0.6 7.8
ns ns CK CK CK CK ns CK CK ns CK CK us
3 3
tDSH tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tPDEX tREFI
4
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. Data sampled at the rising edges of the clock : A0~A11, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. Data latched at both rising and falling edges of Data Strobes(UDQS,LDQS) : DQ, UDM,LDM. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic.
7.
Rev. 0.5 / Jan. 2005
31
HY5DU281622ET
AC CHARACTERISTICS - II
Frequency 400MHz (2.5ns) 375MHz (2.6ns) 350MHz (2.8ns) 333MHz (3.0ns) 300MHz (3.3ns) 275MHz (3.6ns) 250MHz (4.0ns) 200MHz (5.0ns) CL 5 5 4 4 4 4 4 3 tRC 22 21 20 19 18 16 15 12 tRC_APCG 24 23 22 21 20 18 17 13 tRFC 26 25 24 23 22 20 18 14 tRAS 16 15 14 13 12 11 10 8 tRCDRD 6 6 6 6 6 5 5 4 tRCDWR 4 4 4 4 4 3 3 2 tRP 6 6 6 6 6 5 5 4 tDAL 10 10 10 10 10 8 8 7 Unit tCK tCK tCK tCK tCK tCK tCK tCK
Rev. 0.5 / Jan. 2005
32
HY5DU281622ET
CAPACITANCE (TA=25oC, f=1MHz )
Parameter Input Clock Capacitance Input Capacitance Input / Output Capacitance CK, /CK All other input-only pins DQ, DQS, DM Pin Symbol CCK CIN CIO Min 2 2 4 Max 3 3 5 Unit pF pF pF
Note : 1. VDD = min. to max., VDDQ = 2.375V to 2.625V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
RT=50
Output
Zo=50 VREF
CL=30pF
Rev. 0.5 / Jan. 2005
33
HY5DU281622ET PACKAGE INFORMATION
400mil 66pin Thin Small Outline Package
Unit : mm(Inch)
11.94 (0.470) 11.79 (0.462) 10.26 (0.404) 10.05 (0.396) BASE PLANE
22.33 (0.879) 22.12 (0.871)
0 ~ 5 Deg.
0.65 (0.0256) BSC
0.35 (0.0138) 0.25 (0.0098)
SEATING PLANE 0.15 (0.0059) 0.05 (0.0020) 0.597 (0.0235) 0.406 (0.0160) 0.210 (0.0083) 0.120 (0.0047)
1.194 (0.0470) 0.991 (0.0390)
Rev. 0.5 / Jan. 2005
34

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